Axi vdma example

Axi vdma example. When I learn the example of csi2 rx ip on SP701, I feel confused about the data width in vdma data. In this example MM2S portion is disabled and S2MM portion of the VDMA controller has Mar 3, 2014 · Open the base EDK project using Xilinx Platform Studio 14. h, but although they didn't cause any errors, the VDMA did not operate as expected. A video crop is a “cut” of a specific part of the image. However, the same steps could be applied to other Zynq based video designs such as the example from I am currently working with an image processing system. This simulation example shows the data transfer on the MM2S channel. Jul 29, 2021 · This is the interface that the AXI DMA will use to access the DDR (main system memory) of the Arty Z7. vim axicdma. Jan 28, 2019 · This Lecture is part of Udemy Online Course "Video Processing with FPGA". For all other values, the EOLEarlyErr bit gets set instead. Hi, I would like to use the axi-dma core in Linux in simple mode (without scather gatter engine). The current version of this design was created in Vivado 2015. "); Hi everyone, I'mm trying to setup an AXI vdma that writes data from a pattern generator ( ultimately it will be a camera) to a ddr memory and then read Nov 18, 2021 · By Adam Taylor. Once the frame is within the PS domain, we have several processing options available. Double-click on it to open the configuration window and uncheck the box next to The problem is that I have axi_dma and not axi_vdma. If you are having trouble finding the API documentation using the tools, you can find it directly on the Xilinx Wiki. Hact-16, Hact-32, etc). Page generated on 2024-01-11 08:51 EST. If you are using a different PYNQ version you should be able to follow the same steps in Introduction. Viewed 390 times. boot log: [ 1. Optional Scatter Gather DMA support. what we did so far: 1. c does support the AXI Multi-Channel DMA, and I was wondering if there are any examples on how to configure/utilize this driver from the user-space? I've looked into the DMA_Proxy, but all the examples provided are not using MCDMA. It can be configured to have one channel or two channels. Together, the AXI Interconnect and AXI MIG implement a multi-port memory controller (MPMC) for sharing data from multiple sources through a common memory device, typically DDR3 SDRAM. Distributed under the MIT License. In the Python code, two contiguous memory buffers are created using Xlnk. Thanks in advance. Resources Developer Site; Xilinx Wiki; Xilinx Github The AXI Video Direct Memory Access (AXI VDMA) core is a soft AMD IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. Resolved Issues. The DMA will write back to the output_buffer from the AXI stream slave. axistream-connected = <&axi_dma_0>; The AXI VDMA core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025). the kernel we are using has the VDMA support enabled 2. BUT there is a trap to it and it costed me two days to figure that out. This is the second part of a DMA tutorial. c). AXI VDMA IP is configured with only S2MM. The design will be made for a Zynq®-7000 SoC ZC702 Evaluation Kit using the PS DDR. Known Issues. The transfer is cache coherent and when the transfer is complete, the CPU Oct 9, 2017 · The best way to do this would be to use AXI VDMA, as it supports this continuous transfer mode. For more details about the design, refer to the dma_ex_polled/doc directory. This example reads video frames from memory, using Memory Map to Stream (MM2S) interface, and then video frames are written to memory using Stream to Memory Map (S2MM) AXI4 interface. The AXI CDMA provides high-bandwidth Direct Memory Access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol. c" in Vivado v2019. . Address mapping with AXI Video Direct Memory Access and AXI Test Pattern Generator. 2) Enable the upper address range in the Zynq UltraScale+ MPSoC PCW. I have my own IP block with 24 bits input/output axi stream type. This example design builds upon the 'polled mode' example above, adding interrupt-based control of the AXI DMA controller. From the block design of the example, it can be seen that the data width of s_axis_s2mm_tdata is 48. It provides high-bandwidth direct Memory access between memory and AXI4-Stream video type target peripherals including peripherals which support the AXI4-Stream Video protocol as described in the Video IP:AXI Feature Adoption section of the Vivado AXI Reference Guide (UG1037) Nov 23, 2023 · The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. It provides high-bandwidth direct Memory access between memory and AXI4-Stream video type target peripherals including peripherals which support the AXI4-Stream Video protocol as described in the Video IP:AXI Feature Adoption section of the Vivado AXI Reference Guide (UG1037) Saved searches Use saved searches to filter your results more quickly Learn how to use the AXI DMA engine to transfer data between memory and peripherals in a Zynq system. Your screen should look somewhat like the image below. I have managed to write the frames in ddr memory using axi vdma example where it runs a triple frame buffer . But not work. In the Create, manage, and run configurations window, right click on Single Application Debug and click New Configuration. I tried to configure VDMA accroding to the example and datasheet. AXI Video Direct Memory Access (AXI VDMA) 核是一款软 AMD IP 核，可在内存与 AXI4-Stream 类视频目标外设之间提供高带宽直接内存访问该内核通过独立异步读写通道运算提供高效的 2D DMA 运算。初始化、状态、中断及管理寄存器均可通过 AXI4-Lite 从接口进行访问。 All Answers. For more information on creating AXI DMA/VDMA device tree nodes, consult the kernel documentation for them. It is an image processing ip. 550502] xilinx-dpdma fd4c0000. Bit EOLLateErr only gets set if the configured value of HSIZE is a multiple of sixteen less than the actual video received (i. Unfortunately, the driver at the moment has the code to support VDMA, but it does not work. c. dma: Xilinx DPDMA engine is probed [ 1. これは、受信ビデオの一部だけを読み出すことで実現できます。. You will also find examples and tutorials to help you get started with your own projects. The AXI4-Stream data width must be less than or equal to the AXI4 data. This example contains 2 files. Working on a very similar project. The following steps are used to generate the boot image and Linux user-space application. target devices. The CDMA in simple mode is transferring data from the block RAM to the OCM via ACP port. Nov 2, 2023 · The AXI CMDA core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. 551057] Write failed gate address:1000f02 [ 1. 1 the xilinx_dma. No support for linear and hybrid descriptor modes; No Support for Simple DMA mode 43457 - 13. Here is the direct link to the AXI VDMA Standalone Driver source code. 3 - TLAST signal is activated during one pulse every time a complete line has been sent to VDMA. I have designed an IP in Vivado HLS with AXI4-Stream interface for it. Feb 20, 2023 · Description. ビデオクロップとは、イメージの特定の部分を「カット」することです。. The device tree is declaring the VDMA as follows. Independent AXI4 Master interface for optional Scatter/Gather function. Feb 20, 2023 · 1) Set the address width in the AXI DMA Configuration Window to the desired width. I'm trying to use the AXI VDMA to write a 128 x 128 byte section of memory (malloc'd and filled in software) to the AXI Stream bus. Core portion of a program for the transfer is as shown below. 6 PYNQ image and will use Vivado 2020. axivdma triple buffer example. dma: Xilinx AXI VDMA Engine Driver Probed!! [ 1. 73) in PG020 November 30, 2016. I have a 148. Feb 21, 2023 · Example 1 – Video crop using the AXI VDMA IP Video Crop. The CPU initializes the block RAM. Do you have the interrupts of the AXI DMA connected in your vivado design? Is it connected to an A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. The AXI VDMA core supports addressing up to 32 frame buffers for a 32-bit address space. Click the “Add IP” icon and double click “AXI Direct Memory Access” from the catalog. Next, add an instance of the AXI Direct Memory Access IP block to the Vivado block design. It uses simple polling of the status register to manage DMA transfers. In this case VDMA controller control and status registers are mapped at 0x43000000 using AXI-Lite and that memory address can be written to in order to initiate a DMA transfer. The GPO is used to enable the data generator after the software has initialized the DMA. AXI VDMA implements a high-performance, video-optimized DMA engine with frame buffering, and two-dimensional (2D) DMA features. Example 1 – Video crop using the AXI VDMA IP Video Crop. up to 1,024 bits. Connect the interrupts port to an AXI interrupt controller IP AXI VDMA issue with VSIZE. 2 EDK, AXI_DMA - axidma_v4_00_a example 'xaxidma_example_simple_intr. When does AXI VDMA assert s2mm_introut and mm2s_introut outputs? *Does the Interrupt working flow change with Fsync options of the AXI VDMA? ( i. 1. Hello, My Requrement : I have a Custom video IP and Frames need to be written in to SDRAM using AXI VDMA and also Read back the same to stream on any video interface. 1. The AXI VDMA core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The video_out port of a Video In to AXI Stream interface (16 bit tdata) connects to the S_AXI_S2MM port on an AXI VDMA interface (32 bit tdata). This is working fine. com/video-processing-with-fpga/ Nov 20, 2019 · At a high level, it does the same as the AXI VDMA IP we have used in previous entries of the Video Series (Video Series 24, Video Series 25, Video Series 26 ). The Scatter Gather Engine reads the buffer descriptors from the AXI Slave VIP memory model and starts the data transfer. One operation you can do with the AXI Video Direct Memory Access (VDMA) IP is a video crop. c - This file has high level API's to configure and start the VDMA transfer. The 'customize block' dialog does not let me set the tdata width of either interface. . The VDMA is using 8 buffers and circulating through them. - we would like to use the driver which come with the kernel but we need a bit of help. The example design is an excellent place to start and to see an example of how the API is added to an application. I want to stream video using AXI VDMA flow video is captured with hardware Ip and transfered to PS using AXI VDMA, where it is will be transmitted with C application via TCP packet . C_ENABLE_DEBUG_INFO_13 {1}] [get_ips axi_vdma_xyz] Or for IPI: set_property -dict [list CONFIG. xil_printf("Interrupt controller initialization failed. PYNQ DMA tutorial (Part 1: Hardware design) shows how to build the Vivado hardware design used in this notebook. Video Direct Memory Access (VDMA) is one of the key IP blocks used within many image-processing applications. Register Direct Mode. Apr 9, 2020 · #Xilinx #VDMA #Vivado #FPGA #Zynq #VideoProcessingIn this tutorial we see the system level design with Xilinx Video DMA (VDMA) IP and the Xilinx AXI4 Stream May 28, 2014 · The physical address we will pass it through the GP0 port to the AXI VDMA unit so that it knows to which location in the physical DRAM memory (connected to HP0) it should write the incoming image frames. 3) Map the upper addresses in the Address Editor. The IP is connected to the Zynq processing system (PL: xc7z010clg400-1) through another IP AXI_DMA. I am currently trying to do direct bperez77 / xilinx_axidma. c to configure the VDMA I found an example : https://xilinx-wiki. The problem comes with the SDK programming. Each of these designs solves Hello folks, Petalinux 2020. In this Video Series we will see how we can integrate the AXI VDMA IP configured in Triple Buffer Mode into a Video Pipeline in a Vivado design. The advantage of using the uio driver is that you can use also the interrupts of the vdma. Sep 30, 2021 · Another benefit from additional channels is the ability to prioritize the data coming to the DMA. 7. Build the application by selecting it and clicking on the hammer icon: To launch the example application on hardware, right-click on the example design application and click Run As > Run Configurations . How do I get these interfaces connected correctly? [EDIT] The solution given in: Contribute to Digilent/Petalinux-Zybo-Z7-20 development by creating an account on GitHub. 91 Mb Number of DMA Transfers: 1000 transfers Using transmit cha Aug 24, 2023 · The EOLLateErr bit (bit 15) and EOLEarlyErr bit (bit 8) of the VDMA Status Register do not get set correctly. Aug 21, 2018 · The design creates a ping pong buffer (via #pragma HLS DATAFLOW) of user defined length & width. Step 3: petalinux-config --v --get-hw-description=<hdf directory>. Note that the Scatter Gather Engine is enabled for this example, but the Control/Status Stream are disabled. After you can make it work with TPG, then switch back to the real Video stream source of your design. VDMA refers to video DMA which adds mechanisms to handle frame synchronization using ring buffer in DDR, on-the-fly video resolution changes, cropping and zooming. Most of the blocks in Microblaze subsystem (MDM, Local Memory Block, etc) are automatically created and connected by Vivado as part of “Block Automation” and We would like to show you a description here but the site won’t allow us. Please try free run mode, and then see if you can get continuous tready. So why should you use the Video Frame Buffer IP cores and not the AXI VDMA IP? The answer is documented in (Xilinx Answer 72543). The data generator is controller by the tready signal from the DMA together with a general purpose output (GPO) controlled by the software. The prototype is slightly different from the AXI DMA designs by modifying the following: Removing the loopback connection between TX and RX. In the IP catalog, open the “DMA and Timer” branch and find the “AXI DMA Engine” IP core. Design steps: Step 1: Download the attachment and source the zynqmp_axidma_bd. 在此示例中，我要将测试模式生成器 (TPG) IP 用作源，并且将 AXI VDMA IP 配置为已启用读写通道。. Loading Application // Documentation Portal . Up to here everything seems to work. A C++ test bench is included. Based on kernel version 6. I started from Example Project which was set to VSIZE = 1; I have chnaged the Register to 10 but my simulations are not moving forward. The AXI VDMA transfers the 2) VDMA IP register value after the test (check it by "devmem" command) status : 0x001E1001; cmd : 0x001E7090 My system configuration is as follows. Nov 2, 2023 · This example demonstrates how to do video frame transfers in AXI Video DMA loopback mode. Step 2: Create the HDL wrapper and then run synthesis, implementation and generate the bitstream. Click Yes to confirm. Yeah, a lot of the features of the VDMA were hidden to help make the core easier to use for simple double/triple buffer. vdma. This example demonstrates how to use the AXI Video DMA in loopback mode to do video frame transfers. udemy. A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. Independent AXI4-Lite slave interface for register access. In debugging, when break at line 69, contents of memory blocks are not changed. However, when the AXI DMA design was checked via linux DMA engine, axidmatest module did not work properly. The MCDMA test examples provided by Xilinx here are for standalone Connect the S_AXIS_S2MM input of the VDMA to the M_AXIS_MM2S. Thus, it should be connected by VDMA. 通过 AXI VDMA IP 来实现. c - This file comprises sample application to the usage of VDMA API's in vdma_api. vdma ip in csi example for SP701. The buffer swapping shall behave as described in the following: * Input and Output shall run asynchronuously => Input Framerate and Output Framerate can be different. The halted bit (RO) in the S2MM_DMASR register is 0 after 1 second, so there's still something wrong I think. 551154] xilinx-zynqmp-dma I checked possible errors like AXI ID width mismatch, register configuration. 0 works, I hope we can discuss here to see whether there is anyother potential reason to casue AXIs s2mm path stuck in VDMA. to receive from the video device. New Features. For getting this course at $9. Lauri Vosandi blog has this project done xilinx_dma. AXI4 interface for data transfer. AXI VDMA IP を使用した Oct 31, 2023 · Optional AXI burst length is supported for both DST and SRC side. atlassian. 99: https://www. Open the base project in Vivado. So to enable this, have a look at the instructions in Appendix C. Following are the lines I added to beginning of main() function of xhdmi_example. You'd use something like: set_property -dict [list CONFIG. txt. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Mar 16, 2018 · There are four AXI slaves in the design: DDR3 (MIG 7 IP core), UART (AXI Uartlite IP Core), Interrupt Controller (AXI Interrupt Controller) and VDMA (VDMA Control Interface). The advantages are reduced size (compared to AXI Datamover, AXI VDMA) and simplification (no software programming is required to start using). The other thing you need to take care is the Hsize, which is based on the bytes, not pixels/line. Step 4: source the XSA file in PetaLinux and build it. 91 Mb Receive Buffer Size: 7. I try "xaxidma_example_simple_intr. Jun 16, 2020 · I’ll then share several examples of open source AXI masters that can generate burst requests meeting these constraints, progressing from simple to more complex examples along the way. Another advantage is a user configurable processor interrupt that notifies AXI Central DMA Controller. Basically, the AXI VDMA IP takes bytes from the AXI4 Dec 22, 2016 · Modified 7 years, 2 months ago. 550861] xilinx-vdma b0000000. 在这个应用中，我要把 TPG IP 设置为可以生成分辨率为 1024x768 的视频（而会把 HDMI 输出分辨率固定为 800x600 AXI VDMA. The AXI Video Direct Memory Access (VDMA) IP includes two status register, one for the Stream to Memory Mapped (S2MM) interface (responsible for writing data into memory) and one for the Memory Mapped to Stream (MM2S) interface (responsible for reading data from memory) First note that the AXI VDMA includes an example design which is doing pretty much what you are trying to achieve (not using C code but an AXI trafic generator). tcl file in Vivado. vdma_api. However, I still cannot configure it correctly. An optional Scatter Gather (SG) feature can be used to offload control and sequencing Nov 19, 2017 · use dma ip ,the driver,examples worked well, but vdma cant: Z-turn# . e. Hello, *I am confusing about the interrupt workflow of AXI VDMA IP. 1) Devkit version. You will just need to take out the read channel from the code and just use the write channel. petatlinux 2022. 5 MHz clock generated using a clocking wizard that goes to the m_axis* and s_axis* interfaces of the VDMA block and HDMI Tx/Rx subsystems. The AXI VDMA transfers the While the default overlay is sufficient for many use cases, some overlays will require more customisation to provide a user-friendly API. The MM2S is started from the ARM, through the AXILite registers, while the S2MM trigs on TUSER (0). You can use TPG to drive S-AXIS_s2mm of VDMA to evaluate the VDMA behaviour. net/wiki/spaces/A/pages/18842252/AXI+VDMA+Standalone+Driver Where is the example of it？ Introduction. Step 3: Export hardware with the bitstream and get the XSA file. fpga driver xilinx zedboard axi-dma linux Hello, I'm trying to transfer data from AXIS to DDR on SP using AXI VDMA, according to General Use Cases (p. It might worth for you to have a look. System Requirements and Assumptions. Step 1: Create an AXI CDMA user space application using the below command with the attached content (axicdma. If you don't mind running the application an OS . The DMA will read the input_buffer and send the data to the AXI stream master. Jan 14, 2020 · The AXI VDMA core supports the primary AXI4-Stream data bus width of multiples of 8 bits. There is not any example of how to use it, so any help would be apreciated. Supported values are only power of 2 i. Here is my vitis code for the vdma (apologies if it is messy, it is my first time on vitis): * call back happens. Xilinx AXI VDMA engine, it does transfers between memory and video devices. 2 - TVALID signal is activated every time valid data is present on TDATA (31 downto 0) of my core. This example design allocates 4K of block RAM attached to the CPU via M_AXI_GP0. e : different interrupt working in tuser mode, or fsync mode) *Is there a timing diagram that shows the schema of the interrupt Aug 23, 2023 · The data generator creates an incrementing 32 bit data input driving tdata, tlast and tvalid signals for the AXI stream. No support for flow control mode. width for the respective channel. But I did not find any problems. AXI DMA refers to traditional FPGA direct memory access which roughly corresponds to transferring arbitrary streams of bytes from FPGA to a slice of DDR memory and vice versa. The same block RAM is also accessible by the CDMA. This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. In some cases, you might need to have an output resolution which is smaller than the input resolution. This tutorial is based on the v2. /axidma_benchmark -v AXI DMA Benchmark Parameters: Transmit Buffer Size: 7. At the end of transfer it does sanity check and report pass/fail status. At the end of transfer it does sanity check and report pass Oct 13, 2021 · PYNQ DMA tutorial (Part 2: Using the DMA from PYNQ) This tutorial shows how to use the PYNQ DMA class to control an AXI DMA in a hardware design. e 1,2,4,8 and 16; Support 8 DMA Channels; Interrupt Accounting Support. The AXI streams are connected in loopback so that after sending and receiving data via the DMA the contents of the input Apr 17, 2023 · AXI Video Direct Memory Access (VDMA) IP でできる操作のひとつに、ビデオクロップがあります。. The prioritization of channels is highlighted in the AXI MCDMA PG288. My examples will include a virtual FIFO, a memory-backed logic analyzer, a vide frame buffer reader, and a stream to memory DMA. Contains an example on how to use the XAxivdma triple buffer API. This Release Note and Known Issues Answer Record is for the AXI VDMA and contains the following information: General Information. 2, Vitis 2022. SO can you propose me a simple hardware design ? and how i can retrieve the flow video with C code ?. The other AXI DMA settings at the time of test: Buffer Length Register = 14, Allow Unaligned Transfers = Disabled. However, the data widtds of M_axi_mm2s_rdata and M_AXI_S2MM are 64, are these because ? Your approach seems fine so far. c' is incorrect Number of Views 356 57550 - Example Designs - Designing with the AXI DMA core The S2MM channel of the same AXI VDMA IP is getting processed data out of the HLS IP and writing it back to DDR. The block diagram should open and you should only have the Zynq PS in the design. Feb 20, 2023 · Note: It is recommended that you complete the "Using the AXI DMA in polled mode to transfer data to memory" example design from (Xilinx Answer 57561) prior to starting this design. The core provides efficient two dimensional DMA operations with independent asynchronous read and write channel operation. As an example the default AXI GPIO drivers expose channels 1 and 2 as separate attributes meaning that accessing the LEDs in the base overlay requires the following contortion Mar 23, 2022 · The AXI Master VIP configures DMA for Scatter Gather and Cyclic mode, and Scatter Gather Buffer Descriptors would be stored in the AXI Slave VIP core. The datapath is identical to the 'polled I want to use the VDMA IP-core from Xilinx, to implement a typical video triple frame buffer. After boot, I never see axidma as one of the devices. Now we program the VDMA with the obtained physical address for image buffers and rest of the necessary configurations. It allows frames to be moved between the Zynq SoC’s and Zynq UltraScale+ MPSoC’s PS and PL with ease. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. Step 2: petalinux-create -t project -n bram--template zynqMP. Saved searches Use saved searches to filter your results more quickly Description. All the source files for the tutorial are hosted on a GitHub repository and this post is a Hi All, I have a zynq design using the AXI_VDMA under linux working fine, but we are using mmap () instead of using VDMA the driver. Optional Store and Forward support. Optional Data Re-Alignment Engine. EDK will now open the settings for the AXI DMA Engine. Download. Also I checked the axi clock and nothing wrong with it. Nov 23, 2023 · The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. Then it would be great if you could share the ILA capture because this is hard to say without really seeing what is happening. * If the input frame rate on the write channel is faster than the output framerate on This is how the channels are referred to in both the driver and from userspace. Missing Features and known Issues/Limitations in Driver. 2 years ago. I originally tried using the functions defined in xaxivdma. The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. 2; 2) VDMA config (device tree generated by petalinux automatically) axi_vdma_test: dma@a0020000 {#dma-cells = <1>; To carry out this process, the steps I follow are: 1 - Start the transfer with a pulse on TUSER (0) signal on Axi Stream interface. Here is a simple example of the device tree nodes for a system with a single AXI DMA IP, with both a transmit and receive channel. Aug 6, 2014 · Add the AXI DMA. 32 Frame Buffers. Connect the Memory mapped interfaces if not automatically connected. Zynq PS IP configuration window (double-click on Zynq IP block to open). If I increase the Max Burst Size to 128, I get no write transaction overflow. 这与视频系列 24 中的设计相同。. If configured. AXI Video DMA operation problems. This document provides a detailed description of the AXI DMA core, its features, configuration, and performance. The ARM controls DMA transfers via GP ports by accessing the AXI DMA core through its AXI Lite interface. My device tree is configured by the following way: axi_dma_0: axi-dma@40400000 {. In the Flow Navigator, click “Open Block Design”. Both channels are MASTER. 2. The VDMA tdata width is set to 'auto'. If anybody has experience make the VDMA 6. Right click on the AXI DMA Engine and select “Add IP”. fq ch ii kv zf ab wm zx pw km